The paper analyzes and compares main features and performance of two different kinds of active front ends employed in high power induction motor drives. The two considered topologies of Voltage Source Rectifiers (VSR) are: A) two-level four-wire; B) three-level three-wire in Neutral Point Clamped configuration. Reference is made to a Direct Torque Control strategy, which can produce critical unbalanced voltages on dc-link capacitances. Preliminary, the paper describes the control strategies used for both PWM-VSR topologies, suitable to obtain good dynamic performance and high level of power quality indexes. These control techniques are implemented both in simulation software and on a real-time experimental platform linked to a preliminary laboratory test-bench. The corresponding numerical and experimental investigations are carried out in order to highlight and compare performance of the two considered configurations, taking into account also their different circuit complexity. © 2014 IEEE.
Different topologies of active front ends for high power induction motor drives
MARINO, PompeoMembro del Collaboration Group
;RUBINO, LuigiMembro del Collaboration Group
;
2014
Abstract
The paper analyzes and compares main features and performance of two different kinds of active front ends employed in high power induction motor drives. The two considered topologies of Voltage Source Rectifiers (VSR) are: A) two-level four-wire; B) three-level three-wire in Neutral Point Clamped configuration. Reference is made to a Direct Torque Control strategy, which can produce critical unbalanced voltages on dc-link capacitances. Preliminary, the paper describes the control strategies used for both PWM-VSR topologies, suitable to obtain good dynamic performance and high level of power quality indexes. These control techniques are implemented both in simulation software and on a real-time experimental platform linked to a preliminary laboratory test-bench. The corresponding numerical and experimental investigations are carried out in order to highlight and compare performance of the two considered configurations, taking into account also their different circuit complexity. © 2014 IEEE.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
